In a conventional LSI, the elements are integrated in the two-dimensional plane on a silicon substrate. However, the storage capacity of a memory can be increased only by down-sizing (micropatterning) each element. Recently, however, the micropatterning has also become difficult in terms of cost and technique.
To solve the problem, there is proposed an idea of manufacturing a three-dimensionally laminated memory by laminating memory layers three-dimensionally and collectively processing the memory layers. Further, there is proposed a pipe-shaped NAND type flash memory in which a U-shaped NAND string is formed in a laminate direction as the collectively-processed-type three-dimensionally laminated memory. In the pipe-shaped NAND type flash memory, a NAND string is configured of a pair of silicon pillars and a pipe for coupling the silicon pillars in lower ends.
More specifically, memory cell transistors are arranged at the intersections between the silicon pillars and a plurality of stacked word lines. Additionally, select transistors are arranged at the intersections between each of a pair of silicon pillars and two select gates. One of the two select transistors is connected to a bit line, and the other is connected to a source line.
Various manufacturing methods have been proposed as the method of manufacturing the collectively-processed-type three-dimensionally laminated memory.